Energy Efficient and Process Tolerant Full Adder in Technologies Beyond CMOS

This paper presents 1-bit full adder cell in emerging technologies like FinFET and CNFET that operates in the moderate inversion region for energy efficiency, robustness and higher performance. The performance of the adder is improved by the optimum selection of important process parameters like oxide and fin thickness in FinFET and number of carbon nanotubes, chirality vector and pitch in CNFET. The optimized CNFET-based full adder (OP-CNFET) has higher speed, lower PDP (power-delay product) and lower power dissipation as compared to the MOSFET and FinFET full adder cells. The OP-CNFET design also offers tight spread in power, delay and PDP variability against process, voltage and temperature variations. All the evaluations have been carried out using HSPICE simulations based on 32 nm BPTM (Berkeley Predictive Technology Model).